LAB 5

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LAB5edit is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           seg : out  STD_LOGIC_VECTOR (7 downto 1));
end LAB5edit;

architecture Behavioral of LAB5edit is
signal s1 : std_logic;
s2 : std_logic_vector(3 downto 0);
component clk_divider
    Port ( clk_in : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           clk_out : out  STD_LOGIC);
end component clk_divider;

component count10
    Port ( clk : in  STD_LOGIC;
           counter10_out : out  STD_LOGIC_VECTOR(3 downto 0));
end component count10;

component BCD_7segment
    Port ( S : in  STD_LOGIC_VECTOR(3 Downto 0);
           Segs : out  STD_LOGIC_VECTOR(7 DOWNTO 1));
end component BCD_7segment;


begin

U1: clk_divider port map (clk,reset,s1);
U2: count10 port map (s1,s2);
U3: BCD_7segmant port map (s2,seg);

end Behavioral;