LAB 4.1 Edit

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:26:36 07/26/2013 
-- Design Name: 
-- Module Name:    dff - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;




-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dff is
    Port ( d,clk,rst : in  STD_LOGIC;
           q : out  STD_LOGIC);
end dff;

architecture Behavioral of dff is

begin
 process (clk,rst)
begin
if (rst='1')then
q <='0';
elsif (clk'event and clk='1')then
q <= d;
end if;
end process;
end Behavioral;


---------------------------------------------- TB-------------------------------------------


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-- Company: 
-- Engineer:
--
-- Create Date:   18:40:40 07/26/2013
-- Design Name:   
-- Module Name:   D:/3rd years/Digital System Design/D_Flip-Flop/dff_tb.vhd
-- Project Name:  D_Flip-Flop
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: dff
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY dff_tb IS
END dff_tb;
ARCHITECTURE behavior OF dff_tb IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT dff
    PORT(
         d : IN  std_logic;
         clk : IN  std_logic;
         rst : IN  std_logic;
         q : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal d : std_logic := '0';
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';

  --Outputs
   signal q : std_logic;

   -- Clock period definitions
   

BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: dff PORT MAP (
          d => d,
          clk => clk,
          rst => rst,
          q => q
        );



   -- Stimulus process
   stim_proc: process
   begin
d<= not d;
      wait for 100 ns;
clk<= not clk;
      wait for 100 ns;
rst <= not rst;
      wait for 100 ns;



      
   end process;


END;