Experiment III LAB

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:39:29 08/15/2013 
-- Design Name: 
-- Module Name:    HEX_7segs - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity HEX_7segs is
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           seg : out  STD_LOGIC_VECTOR (7 downto 1);
 dg : out  STD_LOGIC);
end HEX_7segs;

architecture Behavioral of HEX_7segs is

begin

process(x)
begin
case x is
WHEN "0000" =>seg<= "1111110";
WHEN "0001" =>seg<= "0110000";
WHEN "0010" =>seg<= "1101101";
WHEN "0011" =>seg<= "1111001";
WHEN "0100" =>seg<= "0110011";
WHEN "0101" =>seg<= "1011011";
WHEN "0110" =>seg<= "1011111";
WHEN "0111" =>seg<= "1110000";
WHEN "1000" =>seg<= "1111111";
WHEN "1001" =>seg<= "1111011";
WHEN "1010" =>seg<= "1111101";
WHEN "1011" =>seg<= "0011111";
WHEN "1100" =>seg<= "1001110";
WHEN "1101" =>seg<= "0111101";
WHEN "1110" =>seg<= "1101111";
WHEN "1111" =>seg<= "1000111";
WHEN OTHERS =>seg<= "0000000";

end case;
end process;
dg <= '0';

end Behavioral;

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NET "x[3]" LOC = P59; 
NET "x[2]" LOC = P60; 
NET "x[1]" LOC = P63; 
NET "x[0]" LOC = P68; 
NET "seg[7]" LOC = P40;
NET "seg[6]" LOC = P35;
NET "seg[5]" LOC = P32;
NET "seg[4]" LOC = P30;
NET "seg[3]" LOC = P27;
NET "seg[2]" LOC = P25;
NET "seg[1]" LOC = P23;
NET "dg" LOC = P31;