Ecperiment IV (Electronics Laboratory)

---------------------------------- TOP Module ----------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:13:33 08/15/2013 
-- Design Name: 
-- Module Name:    top01 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top01 is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           z : out  STD_LOGIC_VECTOR (6 downto 0);
 dg : out  STD_LOGIC;
           carry : out  STD_LOGIC);
end top01;

architecture Behavioral of top01 is

signal s:std_logic_vector(3 downto 0);

component all_01
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           y : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end component;


component HEX_7segs
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           seg : out  STD_LOGIC_VECTOR (7 downto 1);
 dg : out  STD_LOGIC);
end component;

begin
x1: all_01 port map(a,b,s,carry);
x2: HEX_7segs port map (s,z,dg);

end Behavioral;