Ecperiment IV (Electronics Laboratory)

---------------------------------- TOP Module ----------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:13:33 08/15/2013 
-- Design Name: 
-- Module Name:    top01 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top01 is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           z : out  STD_LOGIC_VECTOR (6 downto 0);
 dg : out  STD_LOGIC;
           carry : out  STD_LOGIC);
end top01;

architecture Behavioral of top01 is

signal s:std_logic_vector(3 downto 0);

component all_01
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           y : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end component;


component HEX_7segs
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           seg : out  STD_LOGIC_VECTOR (7 downto 1);
 dg : out  STD_LOGIC);
end component;

begin
x1: all_01 port map(a,b,s,carry);
x2: HEX_7segs port map (s,z,dg);

end Behavioral;

Experiment V (Electronics Laboratory)

-------------------------------------- Clock_Divider --------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_divider is
    Port ( clk_in : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           clk_out : out  STD_LOGIC);
end clk_divider;

architecture Behavioral of clk_divider is

signal temporal: STD_LOGIC;
signal counter : integer range 0 to 12499999:= 0;

begin
frequency_divider: process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (reset ='0') then 
if (counter = 12499999) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1; 
end if;
end if;
end if;
end process;

clk_out <= temporal;

end Behavioral;

-------------------------------------- Counter 10 ------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity count10 is
    Port ( clk : in  STD_LOGIC;
           counter_out : out  STD_LOGIC_VECTOR (3 downto 0));
end count10;
architecture Behavioral of count10 is
signal c : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(clk'EVENT and clk = '1')then
if(c <= 8)then
c <= c +1 ;

else
c <= "0000";
end if ;
end if;
end process;
counter_out <= c;
end Behavioral;

---------------------------------- BCD 7segment ------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BCD_7segment is
    Port ( S : in  STD_LOGIC_VECTOR(3 Downto 0);
           Segs : out  STD_LOGIC_VECTOR(7 DOWNTO 1);
 dg : out std_logic);
end BCD_7segment;

architecture Behavioral of BCD_7segment is

begin
process (S)
begin
case S is
WHEN "0000" =>segs<="1111110";
WHEN "0001" =>segs<="0110000";
WHEN "0010" =>segs<="1101101";
WHEN "0011" =>segs<="1111001";
WHEN "0100" =>segs<="0110011";
WHEN "0101" =>segs<="1011011";
WHEN "0110" =>segs<="1011111";
WHEN "0111" =>segs<="1110000";
WHEN "1000" =>segs<="1111111";
WHEN "1001" =>segs<="1110011";
WHEN OTHERS =>segs<="0000000";

end case;
end process;

dg <= '0';
end Behavioral;

-------------------------------------- TOP Module -------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Exper_5 is

    Port ( clk_system : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           z : out  STD_LOGIC_VECTOR (6 downto 0);

 dg : out std_logic);

end Exper_5;

architecture Behavioral of Exper_5 is

signal int1 : std_logic;

signal int2 : std_logic_vector (3 downto 0);

 

component clk_divider

    Port ( clk_in : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           clk_out : out  STD_LOGIC);

end component;

component count10

    Port ( clk : in  STD_LOGIC;

           counter_out : out  STD_LOGIC_VECTOR (3 downto 0));

end component;

component BCD_7segment

    Port ( S : in  STD_LOGIC_VECTOR(3 Downto 0);

           Segs : out  STD_LOGIC_VECTOR(7 DOWNTO 1);

 dg : out std_logic);

end component;

begin

U1: clk_divider port map (clk_system,reset,int1);

U2: count10 port map (int1,int2);

U3: BCD_7segment port map (int2,z,dg);

end Behavioral;

 -------------------------- UCF ----------------------------------------

NET "clk_system" LOC = P127;

NET "reset" LOC = P44;

NET "z[6]" LOC = P40; #a

NET "z[5]" LOC = P35; #b

NET "z[4]" LOC = P32; #c

NET "z[3]" LOC = P30; #d

NET "z[2]" LOC = P27; #e

NET "z[1]" LOC = P25; #f

NET "z[0]" LOC = P23; #g

NET "dg" LOC = P70;

Experiment III LAB

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:39:29 08/15/2013 
-- Design Name: 
-- Module Name:    HEX_7segs - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity HEX_7segs is
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           seg : out  STD_LOGIC_VECTOR (7 downto 1);
 dg : out  STD_LOGIC);
end HEX_7segs;

architecture Behavioral of HEX_7segs is

begin

process(x)
begin
case x is
WHEN "0000" =>seg<= "1111110";
WHEN "0001" =>seg<= "0110000";
WHEN "0010" =>seg<= "1101101";
WHEN "0011" =>seg<= "1111001";
WHEN "0100" =>seg<= "0110011";
WHEN "0101" =>seg<= "1011011";
WHEN "0110" =>seg<= "1011111";
WHEN "0111" =>seg<= "1110000";
WHEN "1000" =>seg<= "1111111";
WHEN "1001" =>seg<= "1111011";
WHEN "1010" =>seg<= "1111101";
WHEN "1011" =>seg<= "0011111";
WHEN "1100" =>seg<= "1001110";
WHEN "1101" =>seg<= "0111101";
WHEN "1110" =>seg<= "1101111";
WHEN "1111" =>seg<= "1000111";
WHEN OTHERS =>seg<= "0000000";

end case;
end process;
dg <= '0';

end Behavioral;

--------------------------------------------------------------------------------------------

NET "x[3]" LOC = P59; 
NET "x[2]" LOC = P60; 
NET "x[1]" LOC = P63; 
NET "x[0]" LOC = P68; 
NET "seg[7]" LOC = P40;
NET "seg[6]" LOC = P35;
NET "seg[5]" LOC = P32;
NET "seg[4]" LOC = P30;
NET "seg[3]" LOC = P27;
NET "seg[2]" LOC = P25;
NET "seg[1]" LOC = P23;
NET "dg" LOC = P31;

Experiment II _edit LAB

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity haffadd is
    Port ( x : in  STD_LOGIC;
           y : in  STD_LOGIC;
           s : out  STD_LOGIC;
           co : out  STD_LOGIC);
end haffadd;

architecture Behavioral of haffadd is

begin

s <= x xor y;
co <= x and y;

end Behavioral;


----------------------------------------------------------------------------------

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fulladd is
    Port ( x : in  STD_LOGIC;
           y : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           s : out  STD_LOGIC;
           co : out  STD_LOGIC);
end fulladd;

architecture Behavioral of fulladd is

begin

 s <= x xor y  xor cin;
 co <= (x and y) or (cin and x) or (cin and y);


end Behavioral;

------------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity all_01 is
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           y : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end all_01;

architecture Behavioral of all_01 is
signal c1,c2,c3 : std_logic;

component haffadd
    Port ( x : in  STD_LOGIC;
           y : in  STD_LOGIC;
           s : out  STD_LOGIC;
           co : out  STD_LOGIC);
end component;

component fulladd
    Port ( x : in  STD_LOGIC;
           y : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           s : out  STD_LOGIC;
           co : out  STD_LOGIC);
end component;

begin

U1: haffadd port map (x(0),y(0),s(0),c1);
U2: fulladd port map (c1,y(1),x(1),s(1),c2);
U3: fulladd port map (c2,y(2),x(2),s(2),c3);
U4: fulladd port map (c3,y(3),x(3),s(3),cout);

end Behavioral;

Great voice. Like !!

LAB 4.1 Edit

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:26:36 07/26/2013 
-- Design Name: 
-- Module Name:    dff - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;




-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dff is
    Port ( d,clk,rst : in  STD_LOGIC;
           q : out  STD_LOGIC);
end dff;

architecture Behavioral of dff is

begin
 process (clk,rst)
begin
if (rst='1')then
q <='0';
elsif (clk'event and clk='1')then
q <= d;
end if;
end process;
end Behavioral;


---------------------------------------------- TB-------------------------------------------


--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   18:40:40 07/26/2013
-- Design Name:   
-- Module Name:   D:/3rd years/Digital System Design/D_Flip-Flop/dff_tb.vhd
-- Project Name:  D_Flip-Flop
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: dff
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY dff_tb IS
END dff_tb;
ARCHITECTURE behavior OF dff_tb IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT dff
    PORT(
         d : IN  std_logic;
         clk : IN  std_logic;
         rst : IN  std_logic;
         q : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal d : std_logic := '0';
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';

  --Outputs
   signal q : std_logic;

   -- Clock period definitions
   

BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: dff PORT MAP (
          d => d,
          clk => clk,
          rst => rst,
          q => q
        );



   -- Stimulus process
   stim_proc: process
   begin
d<= not d;
      wait for 100 ns;
clk<= not clk;
      wait for 100 ns;
rst <= not rst;
      wait for 100 ns;



      
   end process;


END;

Digital system design

UNIT II Experiment_2

entity Exper_2 is
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           y : in  STD_LOGIC_VECTOR (3 downto 0);
           co : out  STD_LOGIC;
           s : out  STD_LOGIC_VECTOR (3 downto 0));
end Exper_2;

architecture Behavioral of Exper_2 is

component haffadder
    Port ( x : in  STD_LOGIC;
           y : in  STD_LOGIC;
           s : out  STD_LOGIC;
           co : out  STD_LOGIC);
end component;

component fulladder
    Port ( x : in  STD_LOGIC;
           y : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           s : out  STD_LOGIC;
           co : out  STD_LOGIC);
end component;
signal m : STD_LOGIC_VECTOR(2 DOWNTO 0);

begin

U1: haffadd port map (x(0),y(0),s(0),c1);
U2: fulladd port map (c1,y(1),x(1),s(1),c2);
U3: fulladd port map (c2,y(2),x(2),s(2),c3);
U4: fulladd port map (c3,y(3),x(3),s(3),cout);

end Behavioral;

Full & Haff adder

entity fulladder is

    Port ( x : in  STD_LOGIC;

           y : in  STD_LOGIC;

           cin : in  STD_LOGIC;

           s : out  STD_LOGIC;

           co : out  STD_LOGIC);

end fulladder;

architecture Behavioral of fulladder is

begin

s <= x xor y  xor cin;

co <= (x and y) or (cin and x) or (cin and y);

end Behavioral;

--------------------------------------------------------------------------------

entity haffadder is

    Port ( x : in  STD_LOGIC;

           y : in  STD_LOGIC;

           s : out  STD_LOGIC;

           co : out  STD_LOGIC);

end haffadder;

architecture Behavioral of haffadder is

begin

s <= x xor y;

co <= x and y;

end Behavioral;

LAB 5

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LAB5edit is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           seg : out  STD_LOGIC_VECTOR (7 downto 1));
end LAB5edit;

architecture Behavioral of LAB5edit is
signal s1 : std_logic;
s2 : std_logic_vector(3 downto 0);
component clk_divider
    Port ( clk_in : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           clk_out : out  STD_LOGIC);
end component clk_divider;

component count10
    Port ( clk : in  STD_LOGIC;
           counter10_out : out  STD_LOGIC_VECTOR(3 downto 0));
end component count10;

component BCD_7segment
    Port ( S : in  STD_LOGIC_VECTOR(3 Downto 0);
           Segs : out  STD_LOGIC_VECTOR(7 DOWNTO 1));
end component BCD_7segment;


begin

U1: clk_divider port map (clk,reset,s1);
U2: count10 port map (s1,s2);
U3: BCD_7segmant port map (s2,seg);

end Behavioral;

So stupid - -

falls from a height i yesterday, so ache = =

-------------------------- Today --------------------------------

Shopping with my friends

New shoe " NEW BALANCE" and black trousers

Verse of the day " don't give up "