LAB D-FlipFlop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dff is
    Port ( d,clk,rst : in  STD_LOGIC;
           q : out  STD_LOGIC);
end dff;

architecture dff_arch of dff is

begin

process(clk,rst)
begin
if (rst = '1') then
q <= '0';
elsif (clk'event and clk='1') then
q <= d;
End if;
end process;

end dff_arch;

-------------------------- Test Bench ------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY dff_tb IS
END dff_tb;

ARCHITECTURE behavior OF dff_tb IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT dff
    PORT(
         d : IN  std_logic;
         clk : IN  std_logic;
         rst : IN  std_logic;
         q : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal d : std_logic := '0';
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';

  --Outputs
   signal q : std_logic;


BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: dff PORT MAP (
          d => d,
          clk => clk,
          rst => rst,
          q => q
        );

   -- Clock process definitions
   clk_process :process
   begin

   end process;


   -- Stimulus process
   stim_proc: process
   begin

d <= not d;
wait for 100 ns;
clk <= not clk;
wait for 100 ns;
rst <= not rst;

   end process;

END;