LAB 4_2 Count10

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity count10 is
    Port ( clk : in  STD_LOGIC;
           counter10_out : out  STD_LOGIC_VECTOR(3 downto 0));
end count10;

architecture counter10_arch of count10 is
signal counter : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(clk'event and clk ='1') then
if(Counter >=9) then
counter <= "0000";

else
Counter <= Counter +1;

end if;
end if;

end process;

counter10_out <= counter;

end counter10_arch;

---------------------------------- Test Bench ----------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY counter10_tb IS
END counter10_tb;

ARCHITECTURE behavior OF counter10_tb IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT count10
    PORT(
         clk : IN  std_logic;
         counter10_out : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';

  --Outputs
   signal counter10_out : std_logic_vector(3 downto 0);

   -- Clock period definitions


BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: count10 PORT MAP (
          clk => clk,
          counter10_out => counter10_out
        );

   -- Clock process definitions
   clk_process :process
   begin

   end process;


   -- Stimulus process
   stim_proc: process
   begin
      
clk <= not clk;
wait for 100 ns;

   end process;

END;