LAB 2_3 BCD_7Segment

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BCD_7segment is
    Port ( S : in  STD_LOGIC_VECTOR(3 Downto 0);
           Segs : out  STD_LOGIC_VECTOR(7 DOWNTO 1));
end BCD_7segment;

architecture Behavioral of BCD_7segment is

begin
process (S)
begin
case S is
WHEN "0000" =>segs<="1111110";
WHEN "0001" =>segs<="0110000";
WHEN "0010" =>segs<="1101101";
WHEN "0011" =>segs<="1111001";
WHEN "0100" =>segs<="0110011";
WHEN "0101" =>segs<="1011011";
WHEN "0110" =>segs<="1011111";
WHEN "0111" =>segs<="1110000";
WHEN "1000" =>segs<="1111111";
WHEN "1001" =>segs<="1110011";
WHEN OTHERS =>segs<="0000000";

end case;
end process;
end Behavioral;

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY BCD_7Segment_tb IS
END BCD_7Segment_tb;

ARCHITECTURE behavior OF BCD_7Segment_tb IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT BCD_7segment
    PORT(
         S : IN  std_logic_vector(3 downto 0);
         Segs : OUT  std_logic_vector(7 downto 1)
        );
    END COMPONENT;
    

   --Inputs
   signal S : std_logic_vector(3 downto 0) := (others => '0');

  --Outputs
   signal Segs : std_logic_vector(7 downto 1);
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 


BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: BCD_7segment PORT MAP (
          S => S,
          Segs => Segs
        );



   -- Stimulus process
   stim_proc: process
   begin

S <= "0000";
wait for 100 ns;
S <= "0001";
wait for 100 ns;
S <= "0010";
wait for 100 ns;
S <= "0011";
wait for 100 ns;
S <= "0100";
wait for 100 ns;
S <= "0101";
wait for 100 ns;
S <= "0110";
wait for 100 ns;
S <= "0111";
wait for 100 ns;
S <= "1000";
wait for 100 ns;
S <= "1001";
wait for 100 ns;

   end process;

END;