LAB 3 Clock Divider

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_divider is
    Port ( clk_in : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           clk_out : out  STD_LOGIC);
end clk_divider;

architecture Behavioral of clk_divider is

signal temporal: STD_LOGIC;
signal counter : integer range 0 to 12499999:= 0;

begin
frequency_divider: process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = 12499999) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;

clk_out <= temporal;

end Behavioral;


--------------------------------- Test bench -----------------------------------------------


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY clk_divider_tb IS
END clk_divider_tb;

ARCHITECTURE behavior OF clk_divider IS

    COMPONENT clk_divider
    PORT(
         clk_in : IN  std_logic;
         reset : IN  std_logic;
         clk_out : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal clk_in : std_logic := '0';
   signal reset : std_logic := '0';

  --Outputs
   signal clk_out : std_logic;
constant clk_in_t : time :=20 ns;

BEGIN

-- Instantiate of Unit Under Test
   uut: clk200Hz PORT MAP (
          clk_in => clk_in,
          reset => reset,
          clk_out => clk_out
        );

   -- Clock process definitions
   entrada_process :process
begin
clk_in <= '0';
wait for clk_in_t/2;
clk_in <= '1';
wait for clk_in_t/2;
   end process;

   -- processing.
stimuli: process
begin
reset <= '1'; -- Initial conditions.
wait for 100 ns;
reset <= '0'; -- Down to work!

    wait;
   end process;

END;