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LAB 4.1 Edit

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:26:36 07/26/2013 
-- Design Name: 
-- Module Name:    dff - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;




-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dff is
    Port ( d,clk,rst : in  STD_LOGIC;
           q : out  STD_LOGIC);
end dff;

architecture Behavioral of dff is

begin
 process (clk,rst)
begin
if (rst='1')then
q <='0';
elsif (clk'event and clk='1')then
q <= d;
end if;
end process;
end Behavioral;


---------------------------------------------- TB-------------------------------------------


--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   18:40:40 07/26/2013
-- Design Name:   
-- Module Name:   D:/3rd years/Digital System Design/D_Flip-Flop/dff_tb.vhd
-- Project Name:  D_Flip-Flop
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: dff
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY dff_tb IS
END dff_tb;
ARCHITECTURE behavior OF dff_tb IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT dff
    PORT(
         d : IN  std_logic;
         clk : IN  std_logic;
         rst : IN  std_logic;
         q : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal d : std_logic := '0';
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';

  --Outputs
   signal q : std_logic;

   -- Clock period definitions
   

BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: dff PORT MAP (
          d => d,
          clk => clk,
          rst => rst,
          q => q
        );



   -- Stimulus process
   stim_proc: process
   begin
d<= not d;
      wait for 100 ns;
clk<= not clk;
      wait for 100 ns;
rst <= not rst;
      wait for 100 ns;



      
   end process;


END;

Digital system design

UNIT II Experiment_2

entity Exper_2 is
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           y : in  STD_LOGIC_VECTOR (3 downto 0);
           co : out  STD_LOGIC;
           s : out  STD_LOGIC_VECTOR (3 downto 0));
end Exper_2;

architecture Behavioral of Exper_2 is

component haffadder
    Port ( x : in  STD_LOGIC;
           y : in  STD_LOGIC;
           s : out  STD_LOGIC;
           co : out  STD_LOGIC);
end component;

component fulladder
    Port ( x : in  STD_LOGIC;
           y : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           s : out  STD_LOGIC;
           co : out  STD_LOGIC);
end component;
signal m : STD_LOGIC_VECTOR(2 DOWNTO 0);

begin

U1: haffadd port map (x(0),y(0),s(0),c1);
U2: fulladd port map (c1,y(1),x(1),s(1),c2);
U3: fulladd port map (c2,y(2),x(2),s(2),c3);
U4: fulladd port map (c3,y(3),x(3),s(3),cout);

end Behavioral;

Full & Haff adder

entity fulladder is

    Port ( x : in  STD_LOGIC;

           y : in  STD_LOGIC;

           cin : in  STD_LOGIC;

           s : out  STD_LOGIC;

           co : out  STD_LOGIC);

end fulladder;

architecture Behavioral of fulladder is

begin

s <= x xor y  xor cin;

co <= (x and y) or (cin and x) or (cin and y);

end Behavioral;

--------------------------------------------------------------------------------

entity haffadder is

    Port ( x : in  STD_LOGIC;

           y : in  STD_LOGIC;

           s : out  STD_LOGIC;

           co : out  STD_LOGIC);

end haffadder;

architecture Behavioral of haffadder is

begin

s <= x xor y;

co <= x and y;

end Behavioral;

LAB 5

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LAB5edit is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           seg : out  STD_LOGIC_VECTOR (7 downto 1));
end LAB5edit;

architecture Behavioral of LAB5edit is
signal s1 : std_logic;
s2 : std_logic_vector(3 downto 0);
component clk_divider
    Port ( clk_in : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           clk_out : out  STD_LOGIC);
end component clk_divider;

component count10
    Port ( clk : in  STD_LOGIC;
           counter10_out : out  STD_LOGIC_VECTOR(3 downto 0));
end component count10;

component BCD_7segment
    Port ( S : in  STD_LOGIC_VECTOR(3 Downto 0);
           Segs : out  STD_LOGIC_VECTOR(7 DOWNTO 1));
end component BCD_7segment;


begin

U1: clk_divider port map (clk,reset,s1);
U2: count10 port map (s1,s2);
U3: BCD_7segmant port map (s2,seg);

end Behavioral;

So stupid - -

falls from a height i yesterday, so ache = =

-------------------------- Today --------------------------------

Shopping with my friends

New shoe " NEW BALANCE" and black trousers

Verse of the day " don't give up "