UNIT II Experiment_2

entity Exper_2 is
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           y : in  STD_LOGIC_VECTOR (3 downto 0);
           co : out  STD_LOGIC;
           s : out  STD_LOGIC_VECTOR (3 downto 0));
end Exper_2;

architecture Behavioral of Exper_2 is

component haffadder
    Port ( x : in  STD_LOGIC;
           y : in  STD_LOGIC;
           s : out  STD_LOGIC;
           co : out  STD_LOGIC);
end component;

component fulladder
    Port ( x : in  STD_LOGIC;
           y : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           s : out  STD_LOGIC;
           co : out  STD_LOGIC);
end component;
signal m : STD_LOGIC_VECTOR(2 DOWNTO 0);

begin

U1: haffadd port map (x(0),y(0),s(0),c1);
U2: fulladd port map (c1,y(1),x(1),s(1),c2);
U3: fulladd port map (c2,y(2),x(2),s(2),c3);
U4: fulladd port map (c3,y(3),x(3),s(3),cout);

end Behavioral;