Full & Haff adder

entity fulladder is

    Port ( x : in  STD_LOGIC;

           y : in  STD_LOGIC;

           cin : in  STD_LOGIC;

           s : out  STD_LOGIC;

           co : out  STD_LOGIC);

end fulladder;

architecture Behavioral of fulladder is

begin

s <= x xor y  xor cin;

co <= (x and y) or (cin and x) or (cin and y);

end Behavioral;

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entity haffadder is

    Port ( x : in  STD_LOGIC;

           y : in  STD_LOGIC;

           s : out  STD_LOGIC;

           co : out  STD_LOGIC);

end haffadder;

architecture Behavioral of haffadder is

begin

s <= x xor y;

co <= x and y;

end Behavioral;