Full & Haff adder

entity fulladder is

    Port ( x : in  STD_LOGIC;

           y : in  STD_LOGIC;

           cin : in  STD_LOGIC;

           s : out  STD_LOGIC;

           co : out  STD_LOGIC);

end fulladder;

architecture Behavioral of fulladder is

begin

s <= x xor y  xor cin;

co <= (x and y) or (cin and x) or (cin and y);

end Behavioral;

--------------------------------------------------------------------------------

entity haffadder is

    Port ( x : in  STD_LOGIC;

           y : in  STD_LOGIC;

           s : out  STD_LOGIC;

           co : out  STD_LOGIC);

end haffadder;

architecture Behavioral of haffadder is

begin

s <= x xor y;

co <= x and y;

end Behavioral;

LAB 5

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LAB5edit is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           seg : out  STD_LOGIC_VECTOR (7 downto 1));
end LAB5edit;

architecture Behavioral of LAB5edit is
signal s1 : std_logic;
s2 : std_logic_vector(3 downto 0);
component clk_divider
    Port ( clk_in : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           clk_out : out  STD_LOGIC);
end component clk_divider;

component count10
    Port ( clk : in  STD_LOGIC;
           counter10_out : out  STD_LOGIC_VECTOR(3 downto 0));
end component count10;

component BCD_7segment
    Port ( S : in  STD_LOGIC_VECTOR(3 Downto 0);
           Segs : out  STD_LOGIC_VECTOR(7 DOWNTO 1));
end component BCD_7segment;


begin

U1: clk_divider port map (clk,reset,s1);
U2: count10 port map (s1,s2);
U3: BCD_7segmant port map (s2,seg);

end Behavioral;

So stupid - -

falls from a height i yesterday, so ache = =

-------------------------- Today --------------------------------

Shopping with my friends

New shoe " NEW BALANCE" and black trousers

Verse of the day " don't give up "

LAB 4_2 Count10

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity count10 is
    Port ( clk : in  STD_LOGIC;
           counter10_out : out  STD_LOGIC_VECTOR(3 downto 0));
end count10;

architecture counter10_arch of count10 is
signal counter : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(clk'event and clk ='1') then
if(Counter >=9) then
counter <= "0000";

else
Counter <= Counter +1;

end if;
end if;

end process;

counter10_out <= counter;

end counter10_arch;

---------------------------------- Test Bench ----------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY counter10_tb IS
END counter10_tb;

ARCHITECTURE behavior OF counter10_tb IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT count10
    PORT(
         clk : IN  std_logic;
         counter10_out : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';

  --Outputs
   signal counter10_out : std_logic_vector(3 downto 0);

   -- Clock period definitions


BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: count10 PORT MAP (
          clk => clk,
          counter10_out => counter10_out
        );

   -- Clock process definitions
   clk_process :process
   begin

   end process;


   -- Stimulus process
   stim_proc: process
   begin
      
clk <= not clk;
wait for 100 ns;

   end process;

END;

LAB D-FlipFlop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dff is
    Port ( d,clk,rst : in  STD_LOGIC;
           q : out  STD_LOGIC);
end dff;

architecture dff_arch of dff is

begin

process(clk,rst)
begin
if (rst = '1') then
q <= '0';
elsif (clk'event and clk='1') then
q <= d;
End if;
end process;

end dff_arch;

-------------------------- Test Bench ------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY dff_tb IS
END dff_tb;

ARCHITECTURE behavior OF dff_tb IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT dff
    PORT(
         d : IN  std_logic;
         clk : IN  std_logic;
         rst : IN  std_logic;
         q : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal d : std_logic := '0';
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';

  --Outputs
   signal q : std_logic;


BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: dff PORT MAP (
          d => d,
          clk => clk,
          rst => rst,
          q => q
        );

   -- Clock process definitions
   clk_process :process
   begin

   end process;


   -- Stimulus process
   stim_proc: process
   begin

d <= not d;
wait for 100 ns;
clk <= not clk;
wait for 100 ns;
rst <= not rst;

   end process;

END;

LAB 3 Clock Divider

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_divider is
    Port ( clk_in : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           clk_out : out  STD_LOGIC);
end clk_divider;

architecture Behavioral of clk_divider is

signal temporal: STD_LOGIC;
signal counter : integer range 0 to 12499999:= 0;

begin
frequency_divider: process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = 12499999) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;

clk_out <= temporal;

end Behavioral;


--------------------------------- Test bench -----------------------------------------------


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY clk_divider_tb IS
END clk_divider_tb;

ARCHITECTURE behavior OF clk_divider IS

    COMPONENT clk_divider
    PORT(
         clk_in : IN  std_logic;
         reset : IN  std_logic;
         clk_out : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal clk_in : std_logic := '0';
   signal reset : std_logic := '0';

  --Outputs
   signal clk_out : std_logic;
constant clk_in_t : time :=20 ns;

BEGIN

-- Instantiate of Unit Under Test
   uut: clk200Hz PORT MAP (
          clk_in => clk_in,
          reset => reset,
          clk_out => clk_out
        );

   -- Clock process definitions
   entrada_process :process
begin
clk_in <= '0';
wait for clk_in_t/2;
clk_in <= '1';
wait for clk_in_t/2;
   end process;

   -- processing.
stimuli: process
begin
reset <= '1'; -- Initial conditions.
wait for 100 ns;
reset <= '0'; -- Down to work!

    wait;
   end process;

END;

LAB 2_4 Full Adder

AND GATE 2 input

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity AND_2in is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end AND_2in;

architecture Behavioral of AND_2in is

begin

c <= a and b;

end Behavioral;

---------------------------------------------------------------------------------------

OR GATE 2 input

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity OR_2in is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           z : out  STD_LOGIC);
end OR_2in;

architecture Behavioral of OR_2in is

begin
z <= a or b;

end Behavioral;

--------------------------------------------------------------------------------------------------

Haff Adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Haff_add is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           s_ha : out  STD_LOGIC;
           c_ha : out  STD_LOGIC);
end Haff_add;

architecture Behavioral of Haff_add is

begin

S_ha <= a xor b;
c_ha <= a and b;

end Behavioral;

-------------------------------------------------------------------------------------------------

FULL Adder


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Full_add is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c_in : in  STD_LOGIC;
           c_out : out  STD_LOGIC;
           sum : out  STD_LOGIC);
end Full_add;

architecture Behavioral of Full_add is
Signal int1,int2,int3 : STD_LOGIC;
component Haff_add
Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           s_ha : out  STD_LOGIC;
           c_ha : out  STD_LOGIC);

end component;


component OR_2in
port(
a: in STD_LOGIC;
b: in STD_LOGIC;
z: out STD_LOGIC);
end component;
begin
U1 : Haff_add port map (a,b,int2);
U2 : Haff_add port map (int1,c_in,sum,int3);
U3 : OR_2in port map(int3,int2,c_out);


end Behavioral;

-----------------------------------------  Test bench --------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY Full_add_tb IS
END Full_add_tb;

ARCHITECTURE behavior OF Full_add_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Full_add
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         c_in : IN  std_logic;
         c_out : OUT  std_logic;
         sum : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';
   signal c_in : std_logic := '0';

  --Outputs
   signal c_out : std_logic;
   signal sum : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name


BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: Full_add PORT MAP (
          a => a,
          b => b,
          c_in => c_in,
          c_out => c_out,
          sum => sum
        );



   -- Stimulus process
   stim_proc: process
   begin

a <= not a;
wait for 100 ns;
b <= not b;
wait for 100 ns;

   end process;

END;