LAB 2_4 Full Adder

AND GATE 2 input

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity AND_2in is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end AND_2in;

architecture Behavioral of AND_2in is

begin

c <= a and b;

end Behavioral;

---------------------------------------------------------------------------------------

OR GATE 2 input

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity OR_2in is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           z : out  STD_LOGIC);
end OR_2in;

architecture Behavioral of OR_2in is

begin
z <= a or b;

end Behavioral;

--------------------------------------------------------------------------------------------------

Haff Adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Haff_add is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           s_ha : out  STD_LOGIC;
           c_ha : out  STD_LOGIC);
end Haff_add;

architecture Behavioral of Haff_add is

begin

S_ha <= a xor b;
c_ha <= a and b;

end Behavioral;

-------------------------------------------------------------------------------------------------

FULL Adder


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Full_add is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c_in : in  STD_LOGIC;
           c_out : out  STD_LOGIC;
           sum : out  STD_LOGIC);
end Full_add;

architecture Behavioral of Full_add is
Signal int1,int2,int3 : STD_LOGIC;
component Haff_add
Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           s_ha : out  STD_LOGIC;
           c_ha : out  STD_LOGIC);

end component;


component OR_2in
port(
a: in STD_LOGIC;
b: in STD_LOGIC;
z: out STD_LOGIC);
end component;
begin
U1 : Haff_add port map (a,b,int2);
U2 : Haff_add port map (int1,c_in,sum,int3);
U3 : OR_2in port map(int3,int2,c_out);


end Behavioral;

-----------------------------------------  Test bench --------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY Full_add_tb IS
END Full_add_tb;

ARCHITECTURE behavior OF Full_add_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Full_add
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         c_in : IN  std_logic;
         c_out : OUT  std_logic;
         sum : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';
   signal c_in : std_logic := '0';

  --Outputs
   signal c_out : std_logic;
   signal sum : std_logic;
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name


BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: Full_add PORT MAP (
          a => a,
          b => b,
          c_in => c_in,
          c_out => c_out,
          sum => sum
        );



   -- Stimulus process
   stim_proc: process
   begin

a <= not a;
wait for 100 ns;
b <= not b;
wait for 100 ns;

   end process;

END;