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On my way !!

Decode for LAB 6

entity Decode1 is
    Port ( w : in  STD_LOGIC;
 x1 : out STD_LOGIC;
           x2 : out STD_LOGIC);
 
end Decode1;

architecture Behavioral of Decode1 is

begin
process(w)
begin
if (w='1') then
x1 <= '0';
x2 <= '1';
else
x1 <= '1';
x2 <= '0';
end if;
end process;
end Behavioral;

Experiment 6 (Electronics Laboratory)

--------------------------------- clock divider (edit) -------------------------------- entity clk_divider is Port ( clk_in : in STD_LOGIC; reset : in STD_LOGIC; clk_out : out STD_LOGIC); end clk_divider; architecture Behavioral of clk_divider is signal temporal: STD_LOGIC; signal counter : integer range 0 to 2499999:= 0; begin frequency_divider: process (reset, clk_in) begin if (reset = '1') then temporal <= '0'; counter <= 0; elsif rising_edge(clk_in) then if (counter = 2499999) then temporal <= NOT(temporal); counter <= 0; else counter <= counter + 1; end if; end if; end process; clk_out <= temporal; end Behavioral;

------------------------------------------- MUX -------------------------------

entity mux4in is Port ( X : in STD_LOGIC_VECTOR (3 downto 0); Y : in STD_LOGIC_VECTOR (3 downto 0); Co : in STD_LOGIC; S : out STD_LOGIC_VECTOR (3 downto 0)); end mux4in; architecture Behavioral of mux4in is begin process(Co,X,Y) begin case Co is when '1' => S <=X; when others => S <=Y; end case; end process; end Behavioral;

----------------------------------------- TOP -----------------------------------

entity TOP_6 is

    Port ( dip_L,dip_H : in  STD_LOGIC_VECTOR (3 downto 0);

           clk_system : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           seg : out  STD_LOGIC_VECTOR (6 downto 0);

           de1 : out  STD_LOGIC;

           de2 : out  STD_LOGIC);

end TOP_6;

architecture Behavioral of TOP_6 is

component mux4in

    Port ( X : in  STD_LOGIC_VECTOR (3 downto 0);

           Y : in  STD_LOGIC_VECTOR (3 downto 0);

           Co : in  STD_LOGIC;

           S : out  STD_LOGIC_VECTOR (3 downto 0));

end component;

component BCD_7segment

    Port ( S : in  STD_LOGIC_VECTOR(3 Downto 0);

           Segs : out  STD_LOGIC_VECTOR(7 DOWNTO 1);

 dg : out std_logic);

end component;

component clk_divider

    Port ( clk_in : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           clk_out : out  STD_LOGIC);

end component;

component Decode1

    Port ( w : in  STD_LOGIC;

 x1 : out STD_LOGIC;

           x2 : out STD_LOGIC);

end component;

signal int1 : std_logic_vector (3 downto 0);

signal int2 : std_logic;

begin

U1: clk_divider port map (clk_system,reset,int2);

U2: mux4in port map (dip_L,dip_H,int2,int1);

U3: BCD_7segment port map (int1,seg);

U4: Decode1 port map (int2,de1,de2);

end Behavioral;

Ecperiment IV (Electronics Laboratory)

---------------------------------- TOP Module ----------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:13:33 08/15/2013 
-- Design Name: 
-- Module Name:    top01 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top01 is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           z : out  STD_LOGIC_VECTOR (6 downto 0);
 dg : out  STD_LOGIC;
           carry : out  STD_LOGIC);
end top01;

architecture Behavioral of top01 is

signal s:std_logic_vector(3 downto 0);

component all_01
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           y : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           cout : out  STD_LOGIC);
end component;


component HEX_7segs
    Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
           seg : out  STD_LOGIC_VECTOR (7 downto 1);
 dg : out  STD_LOGIC);
end component;

begin
x1: all_01 port map(a,b,s,carry);
x2: HEX_7segs port map (s,z,dg);

end Behavioral;

Experiment V (Electronics Laboratory)

-------------------------------------- Clock_Divider --------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_divider is
    Port ( clk_in : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           clk_out : out  STD_LOGIC);
end clk_divider;

architecture Behavioral of clk_divider is

signal temporal: STD_LOGIC;
signal counter : integer range 0 to 12499999:= 0;

begin
frequency_divider: process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (reset ='0') then 
if (counter = 12499999) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1; 
end if;
end if;
end if;
end process;

clk_out <= temporal;

end Behavioral;

-------------------------------------- Counter 10 ------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity count10 is
    Port ( clk : in  STD_LOGIC;
           counter_out : out  STD_LOGIC_VECTOR (3 downto 0));
end count10;
architecture Behavioral of count10 is
signal c : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(clk'EVENT and clk = '1')then
if(c <= 8)then
c <= c +1 ;

else
c <= "0000";
end if ;
end if;
end process;
counter_out <= c;
end Behavioral;

---------------------------------- BCD 7segment ------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BCD_7segment is
    Port ( S : in  STD_LOGIC_VECTOR(3 Downto 0);
           Segs : out  STD_LOGIC_VECTOR(7 DOWNTO 1);
 dg : out std_logic);
end BCD_7segment;

architecture Behavioral of BCD_7segment is

begin
process (S)
begin
case S is
WHEN "0000" =>segs<="1111110";
WHEN "0001" =>segs<="0110000";
WHEN "0010" =>segs<="1101101";
WHEN "0011" =>segs<="1111001";
WHEN "0100" =>segs<="0110011";
WHEN "0101" =>segs<="1011011";
WHEN "0110" =>segs<="1011111";
WHEN "0111" =>segs<="1110000";
WHEN "1000" =>segs<="1111111";
WHEN "1001" =>segs<="1110011";
WHEN OTHERS =>segs<="0000000";

end case;
end process;

dg <= '0';
end Behavioral;

-------------------------------------- TOP Module -------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Exper_5 is

    Port ( clk_system : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           z : out  STD_LOGIC_VECTOR (6 downto 0);

 dg : out std_logic);

end Exper_5;

architecture Behavioral of Exper_5 is

signal int1 : std_logic;

signal int2 : std_logic_vector (3 downto 0);

 

component clk_divider

    Port ( clk_in : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           clk_out : out  STD_LOGIC);

end component;

component count10

    Port ( clk : in  STD_LOGIC;

           counter_out : out  STD_LOGIC_VECTOR (3 downto 0));

end component;

component BCD_7segment

    Port ( S : in  STD_LOGIC_VECTOR(3 Downto 0);

           Segs : out  STD_LOGIC_VECTOR(7 DOWNTO 1);

 dg : out std_logic);

end component;

begin

U1: clk_divider port map (clk_system,reset,int1);

U2: count10 port map (int1,int2);

U3: BCD_7segment port map (int2,z,dg);

end Behavioral;

 -------------------------- UCF ----------------------------------------

NET "clk_system" LOC = P127;

NET "reset" LOC = P44;

NET "z[6]" LOC = P40; #a

NET "z[5]" LOC = P35; #b

NET "z[4]" LOC = P32; #c

NET "z[3]" LOC = P30; #d

NET "z[2]" LOC = P27; #e

NET "z[1]" LOC = P25; #f

NET "z[0]" LOC = P23; #g

NET "dg" LOC = P70;