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On my way !!

Decode for LAB 6

entity Decode1 is
    Port ( w : in  STD_LOGIC;
 x1 : out STD_LOGIC;
           x2 : out STD_LOGIC);
 
end Decode1;

architecture Behavioral of Decode1 is

begin
process(w)
begin
if (w='1') then
x1 <= '0';
x2 <= '1';
else
x1 <= '1';
x2 <= '0';
end if;
end process;
end Behavioral;

Experiment 6 (Electronics Laboratory)

--------------------------------- clock divider (edit) -------------------------------- entity clk_divider is Port ( clk_in : in STD_LOGIC; reset : in STD_LOGIC; clk_out : out STD_LOGIC); end clk_divider; architecture Behavioral of clk_divider is signal temporal: STD_LOGIC; signal counter : integer range 0 to 2499999:= 0; begin frequency_divider: process (reset, clk_in) begin if (reset = '1') then temporal <= '0'; counter <= 0; elsif rising_edge(clk_in) then if (counter = 2499999) then temporal <= NOT(temporal); counter <= 0; else counter <= counter + 1; end if; end if; end process; clk_out <= temporal; end Behavioral;

------------------------------------------- MUX -------------------------------

entity mux4in is Port ( X : in STD_LOGIC_VECTOR (3 downto 0); Y : in STD_LOGIC_VECTOR (3 downto 0); Co : in STD_LOGIC; S : out STD_LOGIC_VECTOR (3 downto 0)); end mux4in; architecture Behavioral of mux4in is begin process(Co,X,Y) begin case Co is when '1' => S <=X; when others => S <=Y; end case; end process; end Behavioral;

----------------------------------------- TOP -----------------------------------

entity TOP_6 is

    Port ( dip_L,dip_H : in  STD_LOGIC_VECTOR (3 downto 0);

           clk_system : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           seg : out  STD_LOGIC_VECTOR (6 downto 0);

           de1 : out  STD_LOGIC;

           de2 : out  STD_LOGIC);

end TOP_6;

architecture Behavioral of TOP_6 is

component mux4in

    Port ( X : in  STD_LOGIC_VECTOR (3 downto 0);

           Y : in  STD_LOGIC_VECTOR (3 downto 0);

           Co : in  STD_LOGIC;

           S : out  STD_LOGIC_VECTOR (3 downto 0));

end component;

component BCD_7segment

    Port ( S : in  STD_LOGIC_VECTOR(3 Downto 0);

           Segs : out  STD_LOGIC_VECTOR(7 DOWNTO 1);

 dg : out std_logic);

end component;

component clk_divider

    Port ( clk_in : in  STD_LOGIC;

           reset : in  STD_LOGIC;

           clk_out : out  STD_LOGIC);

end component;

component Decode1

    Port ( w : in  STD_LOGIC;

 x1 : out STD_LOGIC;

           x2 : out STD_LOGIC);

end component;

signal int1 : std_logic_vector (3 downto 0);

signal int2 : std_logic;

begin

U1: clk_divider port map (clk_system,reset,int2);

U2: mux4in port map (dip_L,dip_H,int2,int1);

U3: BCD_7segment port map (int1,seg);

U4: Decode1 port map (int2,de1,de2);

end Behavioral;